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Philips Semiconductors
PCF8582C-2
256 × 8-bit CMOS EEPROM with I 2 C-bus interface
td
t r
t HIGH
t f
t LOW
n x 256 + 1
PTC
SDA
SCL
Fig 11. n bytes E/W cycle (n = 2 to 7).
STOP
1
2
MBA698
PTC
td
t r
t HIGH
1
t f
t LOW
2
1153
SDA
SCL
Fig 12. Page mode.
STOP
MBA699
SLAVE ADDRESS
WORD ADDRESS
I C-bus S
2
0A
A
DATA
A
DATA
A P (1)
HIGH
PTC
undefined
undefined
LOW
negative edge
SCL 8-bit
t d
0
1
1
1
2
2
2
257
513
1153
clock (2)
clock (3)
clock (4)
MBA700
(1) If an external clock is chosen, this information is latched internally by setting pin 7 (PTC) LOW after transmission of the
eighth bits of the word address (negative edge of SCL). Thus the state of pin 7 may be previously unde?ned. Leaving pin 7
LOW causes a higher standby current.
(2) 1-byte programming.
(3) 2-byte programming.
(4) One page (8 bytes) programming.
Fig 13. External clock.
9397 750 14222
? Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 25 October 2004
13 of 21
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